ZIW2022_GDDR6_SDL_Optimization_Details
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PartBuilder: SDL Editor Guides

How to use the SDL Editor

  • ZIW2022_GDDR6_SDL_Optimization_Details

    06/09/2022 | 08:16

    we show the rest of the steps we used to optimize the sdl to improve the set of symbols that smart-frac creaeted for the gddr6 dram

    ZIW2022_GDDR6_SDL_Optimization_Details

    Created 06/09/2022
    Chapters
    Transcript
    No chapters

  • Altera/Intel FPGAS: Using sdl loops to define the bank layout

    10/16/2019 | 04:28

    here we show how we can use loops to define multiple banks

    Altera/Intel FPGAS: Using sdl loops to define the bank layout

    Created 10/16/2019

  • Xilinx FPGAS: Using SDL with replicates to create a Larger FPGA

    09/07/2019 | 08:06

    copy the partBuilder config files to a new folder, change the package file to point to new larger FPGA and then simply change the SDL Replicate parameters to build the new part.

    Xilinx FPGAS: Using SDL with replicates to create a Larger FPGA

    Created 09/07/2019

  • Xilinx FPGAS: Replicating FPGA Banks using SDL Editor

    09/07/2019 | 07:43

    How to use the SDL PreProcessor Gui to Wrap a block of SDL Lines with a `REPLICATE loop

    Xilinx FPGAS: Replicating FPGA Banks using SDL Editor

    Created 09/07/2019

  • Using SDL include files with PartBuilder and the SDL-Editor

    04/20/2018 | 06:07

    Using SDL include files with PartBuilder and the SDL-Editor

    Created 04/20/2018
    Chapters
    Transcript
    No chapters

  • Intro to the SDL EDITOR

    10/03/2017 | 14:38

    Intro to the SDL EDITOR

    Created 10/03/2017

  • New SDL Editor HotKeys make editing even more efficient

    04/11/2018 | 02:50

    New SDL Editor HotKeys make editing even more efficient

    Created 04/11/2018

  • Intro to SDL Loops With FPGAs

    03/20/2019 | 01:18

    Recorded Power Point showing how SDL Loops create multiple FPGA bank symbols

    Intro to SDL Loops With FPGAs

    Created 03/20/2019
  • ZIW2022_GDDR6_SDL_Optimization_Details
    06/09/2022 | 08:16
    ZIW2022_GDDR6_SDL_Optimization_Details
    08:16 >

  • Altera/Intel FPGAS: Using sdl loops to define the bank layout
    10/16/2019 | 04:28
    Altera/Intel FPGAS: Using sdl loops to define the bank layout
    04:28 >

  • Xilinx FPGAS: Using SDL with replicates to create a Larger FPGA
    09/07/2019 | 08:06
    Xilinx FPGAS: Using SDL with replicates to create a Larger FPGA
    08:06 >

  • Xilinx FPGAS: Replicating FPGA Banks using SDL Editor
    09/07/2019 | 07:43
    Xilinx FPGAS: Replicating FPGA Banks using SDL Editor
    07:43 >

  • Using SDL include files with PartBuilder and the SDL-Editor
    04/20/2018 | 06:07
    Using SDL include files with PartBuilder and the SDL-Editor
    06:07 >

  • Intro to the SDL EDITOR
    10/03/2017 | 14:38
    Intro to the SDL EDITOR
    14:38 >

  • New SDL Editor HotKeys make editing even more efficient
    04/11/2018 | 02:50
    New SDL Editor HotKeys make editing even more efficient
    02:50 >

  • Intro to SDL Loops With FPGAs
    03/20/2019 | 01:18
    Intro to SDL Loops With FPGAs
    01:18 >