Quick PartBuilder Demo with Altera Max10 324 Pin FPGA

01/04/2020 | 05:07

quick demo of PartBuilder creating symbols for 324 MAX10 device start to finish in under 3 minutes

Altera/Intel FPGAS: Getting the Package Files

10/16/2019 | 02:52

how to get the required Package File from the Altera/Intel Website

Altera/Intel FPGAS: Configure and Read the Altera Package File

10/16/2019 | 03:35

Here we setup and configure PartBuilder to read the selected package from the Altera Package file we downloaded

Altera/Intel FPGAS: Smart-Frac organizes symbols

10/16/2019 | 03:44

here we use smart-frac to create the SDL which organizes the pins into one symbol per bank plus a power symbol

Altera/Intel FPGAS:Editing the SDL to change the symbol layout

10/16/2019 | 07:31

here we edit the sdl to combine IO banks to create fewer symbols

Altera/Intel FPGAS: Using sdl loops to define the bank layout

10/16/2019 | 04:28

here we show how we can use loops to define multiple banks

Altera/Intel FPGAS: Controlling the location of special FPGA PINS

10/20/2019 | 07:26

This video shows how to copy Groups of Pins from the PinExplorer GUI into the SDL Editor as new Pin Matches. It also discusses the 'BEST' modifier on a pinMatch and shows how to easily add the modifier in the SDL-Editor

Building MAX10 Device using ALTERA_PHYSICAL flow Start to Finish

04/26/2018 | 11:58

Building the Altera A10 GX160 672P BGA (10AX016E3F27E2SG)

08/06/2017 | 10:10

This video shows the process of building schematic symbols for the Altera A10 GX160 device in the 672 (F27) package

PartBuilder: Creating Schematic Symbols for Altera ARRIA10 10AX016E3F27E2SG

08/05/2017 | 10:04

This video shows the process of building schematic symbols for the Altera A10 GX160 device in the 672 (F27) package