Using the new Directory Cleanup Tool to get rid of all the extra debug and unneeded files that partBuilder, NetBom, FpgaPinPlanner or other CadEnhance Tools creates
gddr6_build_video_for_ziw2022
Animated Intro to the inner workings of PartBuilder and the PinExtract Smart-Frac and Symbol Description Language
CadEnhance CE-HDL Highlight Reel. Shows the Automation that CE-HDL adds to Cadence Allegro HDL Schematic Capture tool
quick overview of how lockheed would use partBuilder to build symbols for AllegroHdl and Mentor at the same time
Example1 Step 1, Overview of the existing symbol and what we want the final symbol to look like. We go through the new smart-frac process and show the resulting screens
copy the partBuilder config files to a new folder, change the package file to point to new larger FPGA and then simply change the SDL Replicate parameters to build the new part.
How to use the SDL PreProcessor Gui to Wrap a block of SDL Lines with a `REPLICATE loop
Recorded Power Point showing how SDL Loops create multiple FPGA bank symbols
Recorded PowerPoint providing an intro to SDL
This video details all the operations PartBuilder uses to turn the Input PinData into functional schematic Symbols
This shows how the user sets the CE_SITE_DIR enviroment variable (in windows for this case) to point to the directory where a companys site wide settings can be stored