we show the rest of the steps we used to optimize the sdl to improve the set of symbols that smart-frac creaeted for the gddr6 dram
gddr6_build_video_for_ziw2022
Quick Demonstration of all the steps to build this small 26 pin part from Monlithic Power
here we build a 756 Pin Lattice FPGA the LFE5U_85F_xBG756 device. We first create the Pinout Spreadsheet (or Package file) for PartBuilder using the Lattice Diamond tool
quick demo build renesas 9dbl0455 datasheet to symbols in less than 15 minutes
here we show how to quickly build 3 different layouts of an 84 Pin PCIE connector with the Magic of the IS_PIN modifier in SDL
copy the partBuilder config files to a new folder, change the package file to point to new larger FPGA and then simply change the SDL Replicate parameters to build the new part.
How to use the SDL PreProcessor Gui to Wrap a block of SDL Lines with a `REPLICATE loop
Here we show how partBuilder uses to the Zuken Cr5000/8000 Tools to compile the the generated Ascii files and create a valid Zuken Library part